The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As semiconductor device sizes continue to shrink, soft error rate (SER) may become a problem. A soft error is an error caused by a wrong or incorrect signal (for example by noise) within a device, which leads to an incorrect operation of the device, while the device itself may not be defective. A soft error rate is the rate at which the device encounters soft errors. As semiconductor technology nodes progress to newer generations, particularly for devices fabricated under the 65 nanometer (nm) node and beyond, the soft error rate for these devices becomes more pronounced. Current semiconductor fabrication techniques have not proposed an effective method of reducing the soft error rate with respect to the newer technology nodes.
Therefore, while existing methods of soft error rate reduction for semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.